diff -ru gcc-4.2.0/boehm-gc/configure gcc-4.2.0-futaris/boehm-gc/configure
--- gcc-4.2.0/boehm-gc/configure	2007-01-17 18:10:26.000000000 +0000
+++ gcc-4.2.0-futaris/boehm-gc/configure	2007-08-27 14:22:50.000000000 +0100
@@ -4323,7 +4323,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
Only in gcc-4.2.0-futaris/boehm-gc: configure.orig
diff -ru gcc-4.2.0/boehm-gc/include/gc.h gcc-4.2.0-futaris/boehm-gc/include/gc.h
--- gcc-4.2.0/boehm-gc/include/gc.h	2006-09-18 19:45:08.000000000 +0100
+++ gcc-4.2.0-futaris/boehm-gc/include/gc.h	2007-08-27 14:22:51.000000000 +0100
@@ -502,7 +502,7 @@
 #if defined(__linux__) || defined(__GLIBC__)
 # include <features.h>
 # if (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 1 || __GLIBC__ > 2) \
-     && !defined(__ia64__)
+     && !defined(__ia64__) && !defined(__UCLIBC__)
 #   ifndef GC_HAVE_BUILTIN_BACKTRACE
 #     define GC_HAVE_BUILTIN_BACKTRACE
 #   endif
Only in gcc-4.2.0-futaris/boehm-gc/include: gc.h.orig
diff -ru gcc-4.2.0/configure gcc-4.2.0-futaris/configure
--- gcc-4.2.0/configure	2007-05-14 04:19:11.000000000 +0100
+++ gcc-4.2.0-futaris/configure	2007-08-27 14:22:51.000000000 +0100
@@ -3373,7 +3373,7 @@
 # for target_alias and gcc doesn't manage it consistently.
 target_configargs="--cache-file=./config.cache --build=${build_alias} --host=${target_alias} --target=${target_alias} ${target_configargs}"
 
-FLAGS_FOR_TARGET=
+FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET"
 case " $target_configdirs " in
  *" newlib "*)
   case " $target_configargs " in
diff -ru gcc-4.2.0/configure.in gcc-4.2.0-futaris/configure.in
--- gcc-4.2.0/configure.in	2006-12-29 17:47:06.000000000 +0000
+++ gcc-4.2.0-futaris/configure.in	2007-08-27 14:22:51.000000000 +0100
@@ -2080,7 +2080,7 @@
 # for target_alias and gcc doesn't manage it consistently.
 target_configargs="--cache-file=./config.cache --build=${build_alias} --host=${target_alias} --target=${target_alias} ${target_configargs}"
 
-FLAGS_FOR_TARGET=
+FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET"
 case " $target_configdirs " in
  *" newlib "*)
   case " $target_configargs " in
Only in gcc-4.2.0-futaris: configure.in.orig
Only in gcc-4.2.0-futaris: configure.orig
diff -ru gcc-4.2.0/contrib/regression/objs-gcc.sh gcc-4.2.0-futaris/contrib/regression/objs-gcc.sh
--- gcc-4.2.0/contrib/regression/objs-gcc.sh	2005-08-15 01:41:31.000000000 +0100
+++ gcc-4.2.0-futaris/contrib/regression/objs-gcc.sh	2007-08-27 14:22:50.000000000 +0100
@@ -105,6 +105,10 @@
  then
   make all-gdb all-dejagnu all-ld || exit 1
   make install-gdb install-dejagnu install-ld || exit 1
+elif [ $H_REAL_TARGET = $H_REAL_HOST -a $H_REAL_TARGET = i686-pc-linux-uclibc ]
+ then
+  make all-gdb all-dejagnu all-ld || exit 1
+  make install-gdb install-dejagnu install-ld || exit 1
 elif [ $H_REAL_TARGET = $H_REAL_HOST ] ; then
   make bootstrap || exit 1
   make install || exit 1
diff -ru gcc-4.2.0/gcc/config/arm/arm.c gcc-4.2.0-futaris/gcc/config/arm/arm.c
--- gcc-4.2.0/gcc/config/arm/arm.c	2007-03-02 22:03:44.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/config/arm/arm.c	2007-08-27 14:28:08.000000000 +0100
@@ -4,6 +4,7 @@
    Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
    and Martin Simmons (@harleqn.co.uk).
    More major hacks by Richard Earnshaw (rearnsha@arm.com).
+   Cirrus Crunch bugfixes by Vladimir Ivanov (vladit@nucleusys.com)
 
    This file is part of GCC.
 
@@ -131,9 +132,17 @@
 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
 static bool arm_9e_rtx_costs (rtx, int, int, int *);
 static int arm_address_cost (rtx);
-static bool arm_memory_load_p (rtx);
+// static bool arm_memory_load_p (rtx);
 static bool arm_cirrus_insn_p (rtx);
-static void cirrus_reorg (rtx);
+// static void cirrus_reorg (rtx);
+static bool arm_mem_access_p (rtx);
+static bool cirrus_dest_regn_p (rtx, int);
+static rtx cirrus_prev_next_mach_insn (rtx, int *, int);
+static rtx cirrus_prev_mach_insn (rtx, int *);
+static rtx cirrus_next_mach_insn (rtx, int *);
+static void cirrus_reorg_branch (rtx);
+static void cirrus_reorg_bug1 (rtx);
+static void cirrus_reorg_bug10_12 (rtx);
 static void arm_init_builtins (void);
 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
 static void arm_init_iwmmxt_builtins (void);
@@ -427,7 +436,7 @@
 #define FL_STRONG     (1 << 8)	      /* StrongARM */
 #define FL_ARCH5E     (1 << 9)        /* DSP extensions to v5 */
 #define FL_XSCALE     (1 << 10)	      /* XScale */
-#define FL_CIRRUS     (1 << 11)	      /* Cirrus/DSP.  */
+#define FL_CIRRUS     (1 << 11)	      /* Cirrus Crunch coprocessor.  */
 #define FL_ARCH6      (1 << 12)       /* Architecture rel 6.  Adds
 					 media instructions.  */
 #define FL_VFPV2      (1 << 13)       /* Vector Floating Point V2.  */
@@ -491,7 +500,7 @@
 /* Nonzero if this chip is a StrongARM.  */
 int arm_tune_strongarm = 0;
 
-/* Nonzero if this chip is a Cirrus variant.  */
+/* Nonzero if this chip supports Cirrus Crunch coprocessor.  */
 int arm_arch_cirrus = 0;
 
 /* Nonzero if this chip supports Intel Wireless MMX technology.  */
@@ -1193,7 +1202,8 @@
       else
       */
       if (arm_arch_cirrus)
-	arm_fpu_arch = FPUTYPE_MAVERICK;
+        /* Cirrus crunch coprocessor still requires soft-float division.  */
+        arm_fpu_arch = FPUTYPE_MAVERICK;
       else
 	arm_fpu_arch = FPUTYPE_FPA_EMU2;
 #endif
@@ -1578,6 +1588,9 @@
       if (regs_ever_live[regno] && !call_used_regs[regno])
 	return 0;
 
+  if (TARGET_MAVERICK)
+    return 0;
+
   if (TARGET_REALLY_IWMMXT)
     for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
       if (regs_ever_live[regno] && ! call_used_regs [regno])
@@ -3511,7 +3524,7 @@
 
   use_ldrd = (TARGET_LDRD
 	      && (mode == DImode
-		  || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
+		  || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_MAVERICK || TARGET_VFP))));
 
   if (code == POST_INC || code == PRE_DEC
       || ((code == PRE_INC || code == POST_DEC)
@@ -4016,7 +4029,7 @@
 	  /* VFP addressing modes actually allow greater offsets, but for
 	     now we just stick with the lowest common denominator.  */
 	  if (mode == DImode
-	      || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
+	      || ((TARGET_SOFT_FLOAT || TARGET_MAVERICK || TARGET_VFP) && mode == DFmode))
 	    {
 	      low_n = n & 0x0f;
 	      n &= ~0x0f;
@@ -5259,7 +5272,9 @@
   int i;
   REAL_VALUE_TYPE r;
 
-  if (TARGET_VFP)
+  if (TARGET_MAVERICK)
+    fp_consts_inited = 0;
+  else if (TARGET_VFP)
     fp_consts_inited = 1;
   else
     fp_consts_inited = 8;
@@ -5453,41 +5468,6 @@
               || TREE_CODE (valtype) == COMPLEX_TYPE));
 }
 
-/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
-   Use by the Cirrus Maverick code which has to workaround
-   a hardware bug triggered by such instructions.  */
-static bool
-arm_memory_load_p (rtx insn)
-{
-  rtx body, lhs, rhs;;
-
-  if (insn == NULL_RTX || GET_CODE (insn) != INSN)
-    return false;
-
-  body = PATTERN (insn);
-
-  if (GET_CODE (body) != SET)
-    return false;
-
-  lhs = XEXP (body, 0);
-  rhs = XEXP (body, 1);
-
-  lhs = REG_OR_SUBREG_RTX (lhs);
-
-  /* If the destination is not a general purpose
-     register we do not have to worry.  */
-  if (GET_CODE (lhs) != REG
-      || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
-    return false;
-
-  /* As well as loads from memory we also have to react
-     to loads of invalid constants which will be turned
-     into loads from the minipool.  */
-  return (GET_CODE (rhs) == MEM
-	  || GET_CODE (rhs) == SYMBOL_REF
-	  || note_invalid_constants (insn, -1, false));
-}
-
 /* Return TRUE if INSN is a Cirrus instruction.  */
 static bool
 arm_cirrus_insn_p (rtx insn)
@@ -5506,124 +5486,218 @@
   return attr != CIRRUS_NOT;
 }
 
-/* Cirrus reorg for invalid instruction combinations.  */
-static void
-cirrus_reorg (rtx first)
+/* Return TRUE if ISN does memory access.  */
+static bool
+arm_mem_access_p (rtx insn)
 {
-  enum attr_cirrus attr;
-  rtx body = PATTERN (first);
-  rtx t;
-  int nops;
+  enum attr_type attr;
 
-  /* Any branch must be followed by 2 non Cirrus instructions.  */
-  if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
-    {
-      nops = 0;
-      t = next_nonnote_insn (first);
+  /* get_attr aborts on USE and CLOBBER.  */
+  if (!insn
+      || GET_CODE (insn) != INSN
+      || GET_CODE (PATTERN (insn)) == USE
+      || GET_CODE (PATTERN (insn)) == CLOBBER)
+    return 0;
 
-      if (arm_cirrus_insn_p (t))
-	++ nops;
+    attr = get_attr_type (insn);
 
-      if (arm_cirrus_insn_p (next_nonnote_insn (t)))
-	++ nops;
+  return attr == TYPE_LOAD_BYTE
+   || attr == TYPE_LOAD1   || attr == TYPE_LOAD2    || attr == TYPE_LOAD3 || attr == TYPE_LOAD4
+   || attr == TYPE_F_CVT
+   || attr == TYPE_F_MEM_R || attr == TYPE_R_MEM_F  || attr == TYPE_F_2_R || attr == TYPE_R_2_F
+   || attr == TYPE_F_LOAD	|| attr == TYPE_F_LOADS  || attr == TYPE_F_LOADD
+   || attr == TYPE_F_STORE || attr == TYPE_F_STORES || attr == TYPE_F_STORED
+   || attr == TYPE_STORE1  || attr == TYPE_STORE2   || attr == TYPE_STORE3  || attr == TYPE_STORE4;
 
-      while (nops --)
-	emit_insn_after (gen_nop (), first);
+}
 
-      return;
-    }
+/* Return TRUE if destination is certain Cirrus register.  */
+static bool
+cirrus_dest_regn_p (rtx body, int regn)
+{
+  rtx lhs;
+  int reg;
+  lhs = XEXP (body, 0);
+  if (GET_CODE (lhs) != REG)
+    return 0;
 
-  /* (float (blah)) is in parallel with a clobber.  */
-  if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
-    body = XVECEXP (body, 0, 0);
+  reg = REGNO (lhs);
+  if (REGNO_REG_CLASS (reg) != CIRRUS_REGS)
+    return 0;
 
-  if (GET_CODE (body) == SET)
-    {
-      rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
+  return reg == regn;
+}
 
-      /* cfldrd, cfldr64, cfstrd, cfstr64 must
-	 be followed by a non Cirrus insn.  */
-      if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
-	{
-	  if (arm_cirrus_insn_p (next_nonnote_insn (first)))
-	    emit_insn_after (gen_nop (), first);
+/* Get previous/next machine instruction during Cirrus workaround scans.
+   Assume worst case (for the purpose of Cirrus workarounds)
+   for JUMP / CALL instructions.  */
+static rtx
+cirrus_prev_next_mach_insn (rtx insn, int *len, int next)
+{
+  rtx t;
+  int l = 0;
 
-	  return;
-	}
-      else if (arm_memory_load_p (first))
-	{
-	  unsigned int arm_regno;
+  /* It seems that we can count only on INSN length.  */
+  for ( ; ; )
+    {
+      if (next)
+    	insn = NEXT_INSN (insn);
+      else
+    	insn = PREV_INSN (insn);
+      if (!insn)
+    	break;
 
-	  /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
-	     ldr/cfmv64hr combination where the Rd field is the same
-	     in both instructions must be split with a non Cirrus
-	     insn.  Example:
-
-	     ldr r0, blah
-	     nop
-	     cfmvsr mvf0, r0.  */
-
-	  /* Get Arm register number for ldr insn.  */
-	  if (GET_CODE (lhs) == REG)
-	    arm_regno = REGNO (lhs);
-	  else
-	    {
-	      gcc_assert (GET_CODE (rhs) == REG);
-	      arm_regno = REGNO (rhs);
-	    }
+    if (GET_CODE (insn) == INSN)
+      {
+	    l = get_attr_length (insn) / 4;
+        if (l)
+	      break;
+      }
+    else if (GET_CODE (insn) == JUMP_INSN)
+      {
+        l = 1;
+        t = is_jump_table (insn);
+        if (t)
+          l += get_jump_table_size (t) / 4;
+        break;
+      }
+        else if (GET_CODE (insn) == CALL_INSN)
+      {
+        l = 1;
+        break;
+      }
+    }
 
-	  /* Next insn.  */
-	  first = next_nonnote_insn (first);
+  if (len)
+    *len = l;
 
-	  if (! arm_cirrus_insn_p (first))
-	    return;
+  return insn;
+}
 
-	  body = PATTERN (first);
+static rtx
+cirrus_prev_mach_insn (rtx insn, int *len)
+{
+  return cirrus_prev_next_mach_insn (insn, len, 0);
+}
 
-          /* (float (blah)) is in parallel with a clobber.  */
-          if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
-	    body = XVECEXP (body, 0, 0);
-
-	  if (GET_CODE (body) == FLOAT)
-	    body = XEXP (body, 0);
-
-	  if (get_attr_cirrus (first) == CIRRUS_MOVE
-	      && GET_CODE (XEXP (body, 1)) == REG
-	      && arm_regno == REGNO (XEXP (body, 1)))
-	    emit_insn_after (gen_nop (), first);
+static rtx
+cirrus_next_mach_insn (rtx insn, int *len)
+{
+  return cirrus_prev_next_mach_insn (insn, len, 1);
+}
 
-	  return;
-	}
-    }
+/* Cirrus reorg for branch slots.  */
+static void
+cirrus_reorg_branch (rtx insn)
+{
+  rtx t;
+  int nops, l;
 
-  /* get_attr cannot accept USE or CLOBBER.  */
-  if (!first
-      || GET_CODE (first) != INSN
-      || GET_CODE (PATTERN (first)) == USE
-      || GET_CODE (PATTERN (first)) == CLOBBER)
+  /* TODO: handle jump-tables.  */
+  t = is_jump_table (insn);
+  if (t)
     return;
 
-  attr = get_attr_cirrus (first);
-
-  /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
-     must be followed by a non-coprocessor instruction.  */
-  if (attr == CIRRUS_COMPARE)
+  /* Any branch must be followed by 2 non Cirrus instructions.  */
+  t = insn;
+  for (nops = 2; nops > 0; )
     {
-      nops = 0;
+      if (!cirrus_next_mach_insn (t, 0))
+        {
+          insn = t;
+          break;
+        }
+      t = cirrus_next_mach_insn (t, &l);
+      if (arm_cirrus_insn_p (t))
+        break;
+      nops -= l;
 
-      t = next_nonnote_insn (first);
+    }
 
-      if (arm_cirrus_insn_p (t))
-	++ nops;
+  while (nops-- > 0)
+    emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
+}
 
-      if (arm_cirrus_insn_p (next_nonnote_insn (t)))
-	++ nops;
+/* Cirrus reorg for bug #1 (cirrus + cfcmpxx).  */
+static void
+cirrus_reorg_bug1 (rtx insn)
+{
+  rtx body = PATTERN (insn), body2;
+  rtx t;
+  int i, nops, l;
+  enum attr_cirrus attr;
 
-      while (nops --)
-	emit_insn_after (gen_nop (), first);
+  /* Check if destination or clobber is Cirrus register.  */
+  if (GET_CODE (body) == PARALLEL)
+    {
+      for (i = 0; i < XVECLEN (body, 0); i++)
+	  {
+	  body2 = XVECEXP (body, 0, i);
+      if (GET_CODE (body2) == SET)
+        {
+          if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM))
+            {
+		       nops = 5;
+               goto fix;
+            }
+        }
+      else if (GET_CODE (body2) == CLOBBER)
+        {
+          if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM))
+		    {
+		      nops = 4;
+		      goto fix;
+            }
+        }
+      }
+    }
+  else if (GET_CODE (body) == SET)
+    {
+      if (cirrus_dest_regn_p (body, LAST_CIRRUS_FP_REGNUM))
+	  {
+	    nops = 5;
+        goto fix;
+	  }
+    }
+  return;
 
-      return;
+fix:
+  t = insn;
+  for ( ; nops > 0; )
+    {
+      t = cirrus_next_mach_insn (t, &l);
+      if (!t)
+	break;
+      if (GET_CODE (t) == JUMP_INSN
+	  || GET_CODE (t) == CALL_INSN)
+	{
+	  nops -= l;
+	  break;
+	}
+      else if (arm_cirrus_insn_p (t))
+	{
+	  attr = get_attr_cirrus (t);
+	  if (attr == CIRRUS_COMPARE)
+	    break;
+	}
+      nops -= l;
     }
+
+  while (nops-- > 0)
+    emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
+}
+
+/* Cirrus reorg for bugs #10 and #12 (data aborts).  */
+static void
+cirrus_reorg_bug10_12 (rtx insn)
+{
+  rtx t;
+
+  t = cirrus_next_mach_insn (insn, 0);
+  if (arm_cirrus_insn_p (t))
+    if (TARGET_CIRRUS_D0 ||
+	get_attr_cirrus (t) == CIRRUS_DOUBLE)
+      emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
 }
 
 /* Return TRUE if X references a SYMBOL_REF.  */
@@ -7775,7 +7849,7 @@
 {
   Mnode * mp;
   Mnode * nmp;
-  int align64 = 0;
+  int align64 = 0, stuffnop = 0;
 
   if (ARM_DOUBLEWORD_ALIGN)
     for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
@@ -7790,8 +7864,27 @@
 	     ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
 	     INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
 
+  /* Check if branch before minipool is already stuffed with nops.  */
+  if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1)
+    {
+      rtx t;
+
+      t = prev_active_insn (scan);
+      if (GET_CODE (t) != INSN
+	  || PATTERN (t) != const0_rtx)
+	  stuffnop = 1;
+    }
   scan = emit_label_after (gen_label_rtx (), scan);
   scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
+  /* Last instruction was branch, so put two non-Cirrus opcodes.  */
+  if (stuffnop)
+    {
+#if TARGET_CIRRUS /* This is doubling up on nops, so I don't think this is a good idea */
+      emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
+      emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */
+#endif
+    }
+
   scan = emit_label_after (minipool_vector_label, scan);
 
   for (mp = minipool_vector_head; mp != NULL; mp = nmp)
@@ -8206,15 +8299,38 @@
   gcc_assert (GET_CODE (insn) == NOTE);
   minipool_pad = 0;
 
+#if TARGET_CIRRUS /* I think this is a double-up */
+  /* Scan all the insn and fix Cirrus issues.  */
+  if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1)
+    {
+      rtx t, s;
+
+      for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0))
+    if (arm_mem_access_p (t))
+      cirrus_reorg_bug10_12 (t);
+
+      if (TARGET_CIRRUS_D0)
+        for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0))
+      if (arm_cirrus_insn_p (t))
+        cirrus_reorg_bug1 (t);
+
+      /* Find last insn.  */
+      for (t = insn; ; t = s)
+        {
+          s = cirrus_next_mach_insn (t, 0);
+          if (!s)
+            break;
+	    }
+      /* Scan backward and fix branches. - WARNING: appears to cause "bad immediate value for offset" problems! */
+      for ( ; t; t = cirrus_prev_mach_insn (t, 0))
+        if (GET_CODE (t) == JUMP_INSN
+        || GET_CODE (t) == CALL_INSN)
+          cirrus_reorg_branch (t);
+    }
+#endif
   /* Scan all the insns and record the operands that will need fixing.  */
   for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
     {
-      if (TARGET_CIRRUS_FIX_INVALID_INSNS
-          && (arm_cirrus_insn_p (insn)
-	      || GET_CODE (insn) == JUMP_INSN
-	      || arm_memory_load_p (insn)))
-	cirrus_reorg (insn);
-
       if (GET_CODE (insn) == BARRIER)
 	push_minipool_barrier (insn, address);
       else if (INSN_P (insn))
@@ -9880,7 +9996,19 @@
       /* This variable is for the Virtual Frame Pointer, not VFP regs.  */
       int vfp_offset = offsets->frame;
 
-      if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
+      if (arm_fpu_arch == FPUTYPE_MAVERICK)
+    { 
+      for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--)
+        if (regs_ever_live[reg] && !call_used_regs[reg])
+          {
+        floats_offset += 8; /* more problems - futaris? */
+        /* if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) */
+            asm_fprintf (f, "\tnop\n");
+        asm_fprintf (f, "\tcfldrd\tmvd%d, [%r, #-%d]\n",
+                 reg - FIRST_CIRRUS_FP_REGNUM, FP_REGNUM, floats_offset - vfp_offset);
+          }
+    }
+      else if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
 	{
 	  for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
 	    if (regs_ever_live[reg] && !call_used_regs[reg])
@@ -10029,7 +10157,18 @@
 	  output_add_immediate (operands);
 	}
 
-      if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
+      if (arm_fpu_arch == FPUTYPE_MAVERICK)
+    { /* order changed - futaris */
+      for (reg = FIRST_CIRRUS_FP_REGNUM; reg <= LAST_CIRRUS_FP_REGNUM; reg++)
+        if (regs_ever_live[reg] && !call_used_regs[reg])
+          {
+            /* if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) */
+              asm_fprintf (f, "\tnop\n");
+            asm_fprintf (f, "\tcfldrd\tmvd%u, [%r], #8\n",
+                reg - FIRST_CIRRUS_FP_REGNUM, SP_REGNUM);
+	      } /* reg problems - futaris */
+	}
+      else if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
 	{
 	  for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
 	    if (regs_ever_live[reg] && !call_used_regs[reg])
@@ -10530,10 +10669,20 @@
       func_type = arm_current_func_type ();
       if (! IS_VOLATILE (func_type))
 	{
+     /* Space for saved MAVERICK registers.  */
+      if (arm_fpu_arch == FPUTYPE_MAVERICK)
+	{
+	  for (regno = FIRST_CIRRUS_FP_REGNUM; regno <= LAST_CIRRUS_FP_REGNUM; regno++)
+	    if (regs_ever_live[regno] && !call_used_regs[regno])
+	      saved += 8; // 8 in 3.4.3 patch - futaris;
+	}
+      else
 	  /* Space for saved FPA registers.  */
+	{
 	  for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
 	  if (regs_ever_live[regno] && ! call_used_regs[regno])
 	    saved += 12;
+    }
 
 	  /* Space for saved VFP registers.  */
 	  if (TARGET_HARD_FLOAT && TARGET_VFP)
@@ -10825,7 +10974,19 @@
 
       /* Save any floating point call-saved registers used by this
 	 function.  */
-      if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
+      if (arm_fpu_arch == FPUTYPE_MAVERICK)
+    { 
+      for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--)
+        if (regs_ever_live[reg] && !call_used_regs[reg])
+          {
+        insn = gen_rtx_PRE_DEC (DFmode, stack_pointer_rtx); /* think these causes problems */
+        insn = gen_rtx_MEM (DFmode, insn);
+        insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
+                          gen_rtx_REG (DFmode, reg)));
+        RTX_FRAME_RELATED_P (insn) = 1; saved_regs += 8; /* added by futaris */
+	      }
+	}
+      else if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
 	{
 	  for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
 	    if (regs_ever_live[reg] && !call_used_regs[reg])
@@ -11514,26 +11675,53 @@
       /* These encodings assume that AC=1 in the FPA system control
 	 byte.  This allows us to handle all cases except UNEQ and
 	 LTGT.  */
-      switch (comp_code)
-	{
-	case GE: return ARM_GE;
-	case GT: return ARM_GT;
-	case LE: return ARM_LS;
-	case LT: return ARM_MI;
-	case NE: return ARM_NE;
-	case EQ: return ARM_EQ;
-	case ORDERED: return ARM_VC;
-	case UNORDERED: return ARM_VS;
-	case UNLT: return ARM_LT;
-	case UNLE: return ARM_LE;
-	case UNGT: return ARM_HI;
-	case UNGE: return ARM_PL;
-	  /* UNEQ and LTGT do not have a representation.  */
-	case UNEQ: /* Fall through.  */
-	case LTGT: /* Fall through.  */
-	default: gcc_unreachable ();
-	}
-
+    if (!TARGET_MAVERICK)
+    {
+          switch (comp_code)
+    	{
+	    case GE: return ARM_GE;
+    	case GT: return ARM_GT;
+    	case LE: return ARM_LS;
+	    case LT: return ARM_MI;
+    	case NE: return ARM_NE;
+    	case EQ: return ARM_EQ;
+    	case ORDERED: return ARM_VC;
+    	case UNORDERED: return ARM_VS;
+    	case UNLT: return ARM_LT;
+    	case UNLE: return ARM_LE;
+    	case UNGT: return ARM_HI;
+    	case UNGE: return ARM_PL;
+    	  /* UNEQ and LTGT do not have a representation.  */
+	    case UNEQ: /* Fall through.  */
+    	case LTGT: /* Fall through.  */
+    	default: gcc_unreachable ();
+        }
+    }
+    else
+    {
+        /* CIRRUS */
+          switch (comp_code)
+        {
+#if 1
+        case GT: return ARM_VS;
+        case LE: return ARM_LE;
+        case LT: return ARM_LT;
+        case NE: return ARM_NE;
+        case EQ: return ARM_EQ;
+        case UNLE: return ARM_VC;
+        case UNGT: return ARM_GT;
+        case UNGE: return ARM_GE;
+        case UNEQ: return ARM_PL;
+        case LTGT: return ARM_MI;
+        /* These do not have a representation. */
+        case GE: /* Fall through.  -UNGE wrong atm */
+        case UNLT: /* Fall through. -LT wrong atm */
+        case ORDERED: /* Fall through.  -AL wrong atm */
+        case UNORDERED: /* Fall through. -AL wrong atm */
+#endif
+        default: gcc_unreachable (); 
+    	}
+    }
     case CC_SWPmode:
       switch (comp_code)
 	{
@@ -11847,16 +12035,10 @@
 		  || get_attr_conds (this_insn) != CONDS_NOCOND)
 		fail = TRUE;
 
-	      /* A conditional cirrus instruction must be followed by
-		 a non Cirrus instruction.  However, since we
-		 conditionalize instructions in this function and by
-		 the time we get here we can't add instructions
-		 (nops), because shorten_branches() has already been
-		 called, we will disable conditionalizing Cirrus
-		 instructions to be safe.  */
-	      if (GET_CODE (scanbody) != USE
-		  && GET_CODE (scanbody) != CLOBBER
-		  && get_attr_cirrus (this_insn) != CIRRUS_NOT)
+	      /* To avoid erratic behaviour, we avoid conditional Cirrus
+		 instructions when doing workarounds.  */
+	      if (arm_cirrus_insn_p(this_insn)
+    	  && (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1))
 		fail = TRUE;
 	      break;
 
@@ -15283,6 +15465,9 @@
   if (IS_FPA_REGNUM (regno))
     return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
 
+  if (IS_CIRRUS_REGNUM (regno))
+    return 28 + regno - FIRST_CIRRUS_FP_REGNUM;
+
   if (IS_VFP_REGNUM (regno))
     return 64 + regno - FIRST_VFP_REGNUM;
 
Only in gcc-4.2.0-futaris/gcc/config/arm: arm.c.orig
Only in gcc-4.2.0-futaris/gcc/config/arm: arm.c.rej
diff -ru gcc-4.2.0/gcc/config/arm/arm.h gcc-4.2.0-futaris/gcc/config/arm/arm.h
--- gcc-4.2.0/gcc/config/arm/arm.h	2007-03-02 22:03:44.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/config/arm/arm.h	2007-08-27 14:28:08.000000000 +0100
@@ -5,6 +5,7 @@
    and Martin Simmons (@harleqn.co.uk).
    More major hacks by Richard Earnshaw (rearnsha@arm.com)
    Minor hacks by Nick Clifton (nickc@cygnus.com)
+   Cirrus Crunch fixes by Vladimir Ivanov (vladitx@nucleusys.com)
 
    This file is part of GCC.
 
@@ -140,7 +141,9 @@
 %{msoft-float:%{mhard-float:						\
 	%e-msoft-float and -mhard_float may not be used together}}	\
 %{mbig-endian:%{mlittle-endian:						\
-	%e-mbig-endian and -mlittle-endian may not be used together}}"
+	%e-mbig-endian and -mlittle-endian may not be used together}}  \
+%{mfix-crunch-d0:%{mfix-crunch-d1:					\
+	%e-mfix-crunch-d0 and -mfix-crunch-d1 may not be used together}}"
 
 #ifndef CC1_SPEC
 #define CC1_SPEC ""
@@ -179,6 +182,9 @@
 #define TARGET_HARD_FLOAT_ABI		(arm_float_abi == ARM_FLOAT_ABI_HARD)
 #define TARGET_FPA			(arm_fp_model == ARM_FP_MODEL_FPA)
 #define TARGET_MAVERICK			(arm_fp_model == ARM_FP_MODEL_MAVERICK)
+#define TARGET_CIRRUS			(arm_arch_cirrus)
+#define TARGET_CIRRUS_D0		0 /* (target_flags & ARM_FLAG_CIRRUS_D0) */
+#define TARGET_CIRRUS_D1		1 /* (target_flags & ARM_FLAG_CIRRUS_D1) */
 #define TARGET_VFP			(arm_fp_model == ARM_FP_MODEL_VFP)
 #define TARGET_IWMMXT			(arm_arch_iwmmxt)
 #define TARGET_REALLY_IWMMXT		(TARGET_IWMMXT && TARGET_ARM)
diff -ru gcc-4.2.0/gcc/config/arm/arm.md gcc-4.2.0-futaris/gcc/config/arm/arm.md
--- gcc-4.2.0/gcc/config/arm/arm.md	2006-09-27 18:09:40.000000000 +0100
+++ gcc-4.2.0-futaris/gcc/config/arm/arm.md	2007-08-27 14:28:08.000000000 +0100
@@ -3187,34 +3187,37 @@
 
 ;; Fixed <--> Floating conversion insns
 
+;; Maverick Crunch floatsisf2 is buggy - see cirrus.md
 (define_expand "floatsisf2"
   [(set (match_operand:SF           0 "s_register_operand" "")
 	(float:SF (match_operand:SI 1 "s_register_operand" "")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
   "
-  if (TARGET_MAVERICK)
+  if (TARGET_MAVERICK && 0)
     {
       emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
       DONE;
     }
 ")
 
+;; Maverick Crunch floatsidf2 is buggy - see cirrus.md
 (define_expand "floatsidf2"
   [(set (match_operand:DF           0 "s_register_operand" "")
 	(float:DF (match_operand:SI 1 "s_register_operand" "")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
   "
-  if (TARGET_MAVERICK)
+  if (TARGET_MAVERICK && 0)
     {
       emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
       DONE;
     }
 ")
 
+; appears to be buggy for MAVERICK
 (define_expand "fix_truncsfsi2"
   [(set (match_operand:SI         0 "s_register_operand" "")
 	(fix:SI (fix:SF (match_operand:SF 1 "s_register_operand"  ""))))]
-  "TARGET_ARM && TARGET_HARD_FLOAT"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
   "
   if (TARGET_MAVERICK)
     {
@@ -3227,10 +3230,11 @@
     }
 ")
 
+; appears to be buggy for MAVERICK
 (define_expand "fix_truncdfsi2"
   [(set (match_operand:SI         0 "s_register_operand" "")
 	(fix:SI (fix:DF (match_operand:DF 1 "s_register_operand"  ""))))]
-  "TARGET_ARM && TARGET_HARD_FLOAT"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
   "
   if (TARGET_MAVERICK)
     {
@@ -3243,11 +3247,12 @@
 
 ;; Truncation insns
 
+;; Maverick Crunch truncdfsf2 is buggy - see cirrus.md
 (define_expand "truncdfsf2"
   [(set (match_operand:SF  0 "s_register_operand" "")
 	(float_truncate:SF
  	 (match_operand:DF 1 "s_register_operand" "")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
   ""
 )
 
@@ -6982,10 +6987,12 @@
 )
 
 ;; Cirrus DI compare instruction
+;; This is disabled and left go through ARM core registers, because currently
+;; Crunch coprocessor does only signed comparison.
 (define_expand "cmpdi"
   [(match_operand:DI 0 "cirrus_fp_register" "")
    (match_operand:DI 1 "cirrus_fp_register" "")]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0"
   "{
      arm_compare_op0 = operands[0];
      arm_compare_op1 = operands[1];
@@ -6996,7 +7003,7 @@
   [(set (reg:CC CC_REGNUM)
 	(compare:CC (match_operand:DI 0 "cirrus_fp_register" "v")
 		    (match_operand:DI 1 "cirrus_fp_register" "v")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0"
   "cfcmp64%?\\tr15, %V0, %V1"
   [(set_attr "type"   "mav_farith")
    (set_attr "cirrus" "compare")]
@@ -7055,12 +7062,13 @@
   "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
 )
 
+;broken on cirrus
 (define_expand "bge"
   [(set (pc)
 	(if_then_else (ge (match_dup 1) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
-  "TARGET_ARM"
+  "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
   "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
 )
 
@@ -7091,6 +7099,7 @@
   "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
 )
 
+; broken on cirrus?
 (define_expand "bgeu"
   [(set (pc)
 	(if_then_else (geu (match_dup 1) (const_int 0))
@@ -7114,7 +7123,7 @@
 	(if_then_else (unordered (match_dup 1) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0,
 				      arm_compare_op1);"
 )
@@ -7124,7 +7133,7 @@
 	(if_then_else (ordered (match_dup 1) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0,
 				      arm_compare_op1);"
 )
@@ -7134,16 +7143,17 @@
 	(if_then_else (ungt (match_dup 1) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);"
 )
 
+; broken for cirrus
 (define_expand "bunlt"
   [(set (pc)
 	(if_then_else (unlt (match_dup 1) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);"
 )
 
@@ -7152,7 +7162,7 @@
 	(if_then_else (unge (match_dup 1) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);"
 )
 
@@ -7161,7 +7171,7 @@
 	(if_then_else (unle (match_dup 1) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);"
 )
 
@@ -7172,7 +7182,7 @@
 	(if_then_else (uneq (match_dup 1) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);"
 )
 
@@ -7181,7 +7191,7 @@
 	(if_then_else (ltgt (match_dup 1) (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);"
 )
 
@@ -7189,7 +7199,7 @@
 ;; Patterns to match conditional branch insns.
 ;;
 
-; Special pattern to match UNEQ.
+; Special pattern to match UNEQ for FPA and VFP.
 (define_insn "*arm_buneq"
   [(set (pc)
 	(if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
@@ -7205,7 +7215,7 @@
    (set_attr "length" "8")]
 )
 
-; Special pattern to match LTGT.
+; Special pattern to match LTGT for FPA and VFP.
 (define_insn "*arm_bltgt"
   [(set (pc)
 	(if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
@@ -7221,6 +7231,86 @@
    (set_attr "length" "8")]
 )
 
+; Special pattern to match GE for MAVERICK.
+(define_insn "*arm_bge"
+  [(set (pc)
+	(if_then_else (ge (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "*
+  gcc_assert (!arm_ccfsm_state);
+
+  return \"beq\\t%l0\;bvs\\t%l0\"; 
+  "
+  [(set_attr "conds" "jump_clob")
+   (set_attr "length" "8")]
+)
+
+; Special pattern to match GEU for MAVERICK.
+(define_insn "*arm_bgeu"
+  [(set (pc)
+	(if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  "TARGET_ARM && (TARGET_MAVERICK)"
+  "*
+  gcc_assert (!arm_ccfsm_state);
+  if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE)
+      return \"beq\\t%l0\;bvs\\t%l0\"; else return \"bge\\t%l0\;nop\";
+  "
+  [(set_attr "conds" "jump_clob")
+   (set_attr "length" "8")]
+)
+
+; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0.
+(define_insn "*arm_bunlt"
+  [(set (pc)
+	(if_then_else (unlt (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "*
+  gcc_assert (!arm_ccfsm_state);
+
+  return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\";
+  "
+  [(set_attr "conds" "jump_clob")
+   (set_attr "length" "12")]
+)
+
+; Special pattern to match UNORDERED for MAVERICK - UGLY since we need to test for Z=0 && N=0.
+(define_insn "*arm_bunordered"
+  [(set (pc)
+	(if_then_else (unordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+  "*
+  gcc_assert (!arm_ccfsm_state);
+
+  return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\";
+  "
+  [(set_attr "conds" "jump_clob")
+   (set_attr "length" "12")]
+)
+
+; Special pattern to match ORDERED for MAVERICK.
+(define_insn "*arm_bordered"
+  [(set (pc)
+	(if_then_else (ordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+  "*
+  gcc_assert (!arm_ccfsm_state);
+
+  return \"beq\\t%l0\;bmi\\t%l0\";
+  "
+  [(set_attr "conds" "jump_clob")
+   (set_attr "length" "8")]
+)
+
 (define_insn "*arm_cond_branch"
   [(set (pc)
 	(if_then_else (match_operator 1 "arm_comparison_operator"
@@ -7240,7 +7330,7 @@
    (set_attr "type" "branch")]
 )
 
-; Special pattern to match reversed UNEQ.
+; Special pattern to match reversed UNEQ for FPA and VFP.
 (define_insn "*arm_buneq_reversed"
   [(set (pc)
 	(if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0))
@@ -7256,7 +7346,7 @@
    (set_attr "length" "8")]
 )
 
-; Special pattern to match reversed LTGT.
+; Special pattern to match reversed LTGT for FPA and VFP.
 (define_insn "*arm_bltgt_reversed"
   [(set (pc)
 	(if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0))
@@ -7272,6 +7362,86 @@
    (set_attr "length" "8")]
 )
 
+; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0.
+(define_insn "*arm_bge_reversed"
+  [(set (pc)
+	(if_then_else (ge (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+              (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "*
+  gcc_assert (!arm_ccfsm_state);
+
+  return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\";
+  "
+  [(set_attr "conds" "jump_clob")
+   (set_attr "length" "12")]
+)
+
+; Special pattern to match reversed GEU for MAVERICK.
+(define_insn "*arm_bgeu_reversed"
+  [(set (pc)
+	(if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0))
+              (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  "TARGET_ARM && (TARGET_MAVERICK)"
+  "*
+  gcc_assert (!arm_ccfsm_state);
+
+  return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\";
+  "
+  [(set_attr "conds" "jump_clob")
+   (set_attr "length" "12")]
+)
+
+; Special pattern to match reversed UNLT for MAVERICK.
+(define_insn "*arm_bunlt_reversed"
+  [(set (pc)
+	(if_then_else (unlt (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+              (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "*
+  gcc_assert (!arm_ccfsm_state);
+
+  return \"beq\\t%l0\;bvs\\t%l0\";
+  "
+  [(set_attr "conds" "jump_clob")
+   (set_attr "length" "8")]
+)
+
+; Special pattern to match reversed UNORDERED for MAVERICK.
+(define_insn "*arm_bunordered_reversed"
+  [(set (pc)
+	(if_then_else (unordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+              (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+  "*
+  gcc_assert (!arm_ccfsm_state);
+
+  return \"beq\\t%l0\;bmi\\t%l0\";
+  "
+  [(set_attr "conds" "jump_clob")
+   (set_attr "length" "8")]
+)
+
+; Special pattern to match reversed ORDERED for MAVERICK - UGLY since we need to test for Z=0 && N=0.
+(define_insn "*arm_bordered_reversed"
+  [(set (pc)
+	(if_then_else (ordered (match_operand:CCFP 1 "cc_register" "") (const_int 0))
+              (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+  "*
+  gcc_assert (!arm_ccfsm_state);
+
+  return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\";
+  "
+  [(set_attr "conds" "jump_clob")
+   (set_attr "length" "12")]
+)
+
 (define_insn "*arm_cond_branch_reversed"
   [(set (pc)
 	(if_then_else (match_operator 1 "arm_comparison_operator"
@@ -7323,13 +7493,22 @@
   "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
 )
 
+;; broken for cirrus - definitely
 (define_expand "sge"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(ge:SI (match_dup 1) (const_int 0)))]
-  "TARGET_ARM"
+  "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
 )
 
+;;; DO NOT add patterns for SGE these can not be represented with MAVERICK
+; (define_expand "sge"
+;   [(set (match_operand:SI 0 "s_register_operand" "")
+; 	(ge:SI (match_dup 1) (const_int 0)))]
+;   "TARGET_ARM && (TARGET_MAVERICK)"
+;   "gcc_unreachable ();"
+; )
+
 (define_expand "slt"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(lt:SI (match_dup 1) (const_int 0)))]
@@ -7351,6 +7530,7 @@
   "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
 )
 
+;; broken for cirrus - maybe
 (define_expand "sgeu"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(geu:SI (match_dup 1) (const_int 0)))]
@@ -7358,6 +7538,14 @@
   "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);"
 )
 
+;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK?
+; (define_expand "sgeu"
+;  [(set (match_operand:SI 0 "s_register_operand" "")
+; 	(ge:SI (match_dup 1) (const_int 0)))]
+;   "TARGET_ARM && (TARGET_MAVERICK)"
+;   "gcc_unreachable ();"
+; )
+
 (define_expand "sltu"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(ltu:SI (match_dup 1) (const_int 0)))]
@@ -7384,7 +7572,7 @@
 (define_expand "sungt"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(ungt:SI (match_dup 1) (const_int 0)))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0,
 				      arm_compare_op1);"
 )
@@ -7392,11 +7580,12 @@
 (define_expand "sunge"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(unge:SI (match_dup 1) (const_int 0)))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0,
 				      arm_compare_op1);"
 )
 
+; broken for cirrus
 (define_expand "sunlt"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(unlt:SI (match_dup 1) (const_int 0)))]
@@ -7405,14 +7594,38 @@
 				      arm_compare_op1);"
 )
 
+;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK
+; (define_expand "sunlt"
+;   [(set (match_operand:SI 0 "s_register_operand" "")
+; 	(unlt:SI (match_dup 1) (const_int 0)))]
+;   "TARGET_ARM && (TARGET_MAVERICK)"
+;   "gcc_unreachable ();"
+; )
+
 (define_expand "sunle"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(unle:SI (match_dup 1) (const_int 0)))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
   "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0,
 				      arm_compare_op1);"
 )
 
+;(define_expand "suneq"
+;  [(set (match_operand:SI 0 "s_register_operand" "")
+;	(uneq:SI (match_dup 1) (const_int 0)))]
+;  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+;  "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0,
+;				      arm_compare_op1);"
+;)
+
+;(define_expand "sltgt"
+;  [(set (match_operand:SI 0 "s_register_operand" "")
+;	(ltgt:SI (match_dup 1) (const_int 0)))]
+;  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)"
+;  "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0,
+;				      arm_compare_op1);"
+;)
+
 ;;; DO NOT add patterns for SUNEQ or SLTGT, these can't be represented with
 ;;; simple ARM instructions. 
 ;
@@ -7474,7 +7687,7 @@
     enum rtx_code code = GET_CODE (operands[1]);
     rtx ccreg;
 
-    if (code == UNEQ || code == LTGT)
+    if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED)))
       FAIL;
 
     ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
@@ -7493,7 +7706,8 @@
     enum rtx_code code = GET_CODE (operands[1]);
     rtx ccreg;
 
-    if (code == UNEQ || code == LTGT)
+    if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED)))
+ 
       FAIL;
 
     /* When compiling for SOFT_FLOAT, ensure both arms are in registers. 
@@ -7512,13 +7726,13 @@
 	(if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
 			 (match_operand:DF 2 "s_register_operand" "")
 			 (match_operand:DF 3 "arm_float_add_operand" "")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
+  "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)"
   "
   {
     enum rtx_code code = GET_CODE (operands[1]);
     rtx ccreg;
 
-    if (code == UNEQ || code == LTGT)
+    if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED)))
       FAIL;
 
     ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
@@ -9736,7 +9950,7 @@
   return arm_output_epilogue (next_nonnote_insn (insn));
   "
 ;; Length is absolute worst case
-  [(set_attr "length" "44")
+  [(set_attr "length" "108")
    (set_attr "type" "block")
    ;; We don't clobber the conditions, but the potential length of this
    ;; operation is sufficient to make conditionalizing the sequence 
@@ -9754,7 +9968,7 @@
     return thumb_unexpanded_epilogue ();
   "
   ; Length is absolute worst case
-  [(set_attr "length" "44")
+  [(set_attr "length" "108")
    (set_attr "type" "block")
    ;; We don't clobber the conditions, but the potential length of this
    ;; operation is sufficient to make conditionalizing the sequence 
@@ -10208,13 +10422,73 @@
   "TARGET_ARM && arm_arch5e"
   "pld\\t%a0")
 
+;; Special predication pattern for Maverick Crunch floating-point
+
+(define_cond_exec
+  [(match_operator 0 "maverick_comparison_operator"
+    [(match_operand:CCFP 1 "cc_register" "")
+     (const_int 0)])]
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  ""
+)
+
+;; Special predication pattern for Maverick Crunch - !CCFP
+
+(define_cond_exec
+  [(match_operator 0 "arm_comparison_operator"
+    [(match_operand:CC_NOOV 1 "cc_register" "")
+     (const_int 0)])]
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  ""
+)
+
+(define_cond_exec
+  [(match_operator 0 "arm_comparison_operator"
+    [(match_operand:CC_Z 1 "cc_register" "")
+     (const_int 0)])]
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  ""
+)
+
+(define_cond_exec
+  [(match_operator 0 "arm_comparison_operator"
+    [(match_operand:CC_SWP 1 "cc_register" "")
+     (const_int 0)])]
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  ""
+)
+
+(define_cond_exec
+  [(match_operator 0 "arm_comparison_operator"
+    [(match_operand:CC_C 1 "cc_register" "")
+     (const_int 0)])]
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  ""
+)
+
+(define_cond_exec
+  [(match_operator 0 "arm_comparison_operator"
+    [(match_operand:CC_N 1 "cc_register" "")
+     (const_int 0)])]
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  ""
+)
+
+(define_cond_exec
+  [(match_operator 0 "arm_comparison_operator"
+    [(match_operand:CC 1 "cc_register" "")
+     (const_int 0)])]
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  ""
+)
+
 ;; General predication pattern
 
 (define_cond_exec
   [(match_operator 0 "arm_comparison_operator"
     [(match_operand 1 "cc_register" "")
      (const_int 0)])]
-  "TARGET_ARM"
+  "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
   ""
 )
 
@@ -10222,6 +10496,7 @@
   [(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_PROLOGUE_USE)]
   ""
   "%@ %0 needed for prologue"
+  [(set_attr "length" "0")]
 )
 
 
Only in gcc-4.2.0-futaris/gcc/config/arm: arm.md.orig
diff -ru gcc-4.2.0/gcc/config/arm/arm.opt gcc-4.2.0-futaris/gcc/config/arm/arm.opt
--- gcc-4.2.0/gcc/config/arm/arm.opt	2006-05-17 20:19:02.000000000 +0100
+++ gcc-4.2.0-futaris/gcc/config/arm/arm.opt	2007-08-27 14:28:08.000000000 +0100
@@ -68,6 +68,14 @@
 Target Report Mask(CIRRUS_FIX_INVALID_INSNS)
 Cirrus: Place NOPs to avoid invalid instruction combinations
 
+fix-crunch-d0
+Target Report Mask(ARM_FLAG_CIRRUS_D0)
+Cirrus: workarounds for Crunch coprocessor revision D0
+
+fix-crunch-d1
+Target Report Mask(ARM_FLAG_CIRRUS_D1)
+Cirrus: workarounds for Crunch coprocessor revision D1
+
 mcpu=
 Target RejectNegative Joined
 Specify the name of the target CPU
diff -ru gcc-4.2.0/gcc/config/arm/cirrus.md gcc-4.2.0-futaris/gcc/config/arm/cirrus.md
--- gcc-4.2.0/gcc/config/arm/cirrus.md	2005-06-25 02:22:41.000000000 +0100
+++ gcc-4.2.0-futaris/gcc/config/arm/cirrus.md	2007-08-27 14:28:08.000000000 +0100
@@ -255,18 +255,20 @@
   [(set_attr "cirrus" "normal")]
 )
 
+;; appears to be buggy: neg 0 != -0
 (define_insn "*cirrus_negsf2"
   [(set (match_operand:SF         0 "cirrus_fp_register" "=v")
 	(neg:SF (match_operand:SF 1 "cirrus_fp_register"  "v")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
   "cfnegs%?\\t%V0, %V1"
   [(set_attr "cirrus" "normal")]
 )
 
+;; appears to be buggy: neg 0 != -0
 (define_insn "*cirrus_negdf2"
   [(set (match_operand:DF         0 "cirrus_fp_register" "=v")
 	(neg:DF (match_operand:DF 1 "cirrus_fp_register"  "v")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
   "cfnegd%?\\t%V0, %V1"
   [(set_attr "cirrus" "normal")]
 )
@@ -298,21 +300,23 @@
 )
 
 ;; Convert Cirrus-SI to Cirrus-SF
+; appears to be buggy
 (define_insn "cirrus_floatsisf2"
   [(set (match_operand:SF           0 "cirrus_fp_register" "=v")
  	(float:SF (match_operand:SI 1 "s_register_operand"  "r")))
    (clobber (match_scratch:DF 2 "=v"))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
   "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
   [(set_attr "length" "8")
    (set_attr "cirrus" "move")]
 )
 
+;appears to be buggy
 (define_insn "cirrus_floatsidf2"
   [(set (match_operand:DF           0 "cirrus_fp_register" "=v")
 	(float:DF (match_operand:SI 1 "s_register_operand" "r")))
    (clobber (match_scratch:DF 2 "=v"))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
   "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
   [(set_attr "length" "8")
    (set_attr "cirrus" "move")]
@@ -321,41 +325,45 @@
 (define_insn "floatdisf2"
   [(set (match_operand:SF           0 "cirrus_fp_register" "=v")
 	(float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
   "cfcvt64s%?\\t%V0, %V1"
   [(set_attr "cirrus" "normal")])
 
 (define_insn "floatdidf2"
   [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
 	(float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
   "cfcvt64d%?\\t%V0, %V1"
   [(set_attr "cirrus" "normal")])
 
+; appears to be buggy
 (define_insn "cirrus_truncsfsi2"
   [(set (match_operand:SI         0 "s_register_operand" "=r")
 	(fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register"  "v"))))
    (clobber (match_scratch:DF     2                      "=v"))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
   "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
   [(set_attr "length" "8")
    (set_attr "cirrus" "normal")]
 )
 
+; appears to be buggy
 (define_insn "cirrus_truncdfsi2"
   [(set (match_operand:SI         0 "s_register_operand" "=r")
 	(fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register"  "v"))))
    (clobber (match_scratch:DF     2                      "=v"))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
   "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
-  [(set_attr "length" "8")]
+  [(set_attr "length" "8")
+   (set_attr "cirrus" "normal")]
 )
 
+; appears to be buggy - causes 20000320-1.c to fail in execute/ieee
 (define_insn "*cirrus_truncdfsf2"
   [(set (match_operand:SF  0 "cirrus_fp_register" "=v")
         (float_truncate:SF
          (match_operand:DF 1 "cirrus_fp_register" "v")))]
-  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
   "cfcvtds%?\\t%V0, %V1"
   [(set_attr "cirrus" "normal")]
 )
Only in gcc-4.2.0-futaris/gcc/config/arm: cirrus.md.orig
diff -ru gcc-4.2.0/gcc/config/arm/ieee754-df.S gcc-4.2.0-futaris/gcc/config/arm/ieee754-df.S
--- gcc-4.2.0/gcc/config/arm/ieee754-df.S	2007-01-09 10:11:53.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/config/arm/ieee754-df.S	2007-08-27 14:28:07.000000000 +0100
@@ -42,8 +42,9 @@
 
 
 @ For FPA, float words are always big-endian.
+@ For MAVERICK, float words are always little-endian.
 @ For VFP, floats words follow the memory system mode.
-#if defined(__VFP_FP__) && !defined(__ARMEB__)
+#if ((defined(__VFP_FP__) && !defined(__ARMEB__)) || defined(__MAVERICK__))
 #define xl r0
 #define xh r1
 #define yl r2
@@ -451,8 +452,13 @@
 
 	orrs	r2, r0, r1
 #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPA_FP__)
 	mvfeqd	f0, #0.0
 #endif
+#if defined (__MAVERICK__)
+    cfstrd  mvd0, #0.0
+#endif
+#endif
 	RETc(eq)
 
 #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
@@ -473,8 +479,13 @@
 
 	orrs	r2, r0, r1
 #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPA_FP__)
 	mvfeqd	f0, #0.0
 #endif
+#if defined (__MAVERICK__)
+    cfstrd  mvd0, #0.0
+#endif
+#endif
 	RETc(eq)
 
 #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
@@ -526,8 +537,14 @@
 	@ Legacy code expects the result to be returned in f0.  Copy it
 	@ there as well.
 LSYM(f0_ret):
+#if defined (__FPA_FP__)
 	stmfd	sp!, {r0, r1}
 	ldfd	f0, [sp], #8
+#endif
+#if defined (__MAVERICK__)
+    cfmvdlr  mvd0, xl
+    cfmvdhr  mvd0, xh
+#endif
 	RETLDM
 
 #endif
@@ -700,6 +717,10 @@
 	cmn	r4, #(53 + 1)
 	movle	xl, #0
 	bicle	xh, xh, #0x7fffffff
+#ifdef __MAVERICK__
+    cfmvdlr mvd0, xl
+    cfmvdhr mvd0, xh
+#endif
 	RETLDM	"r4, r5, r6" le
 
 	@ Find out proper shift value.
@@ -721,6 +742,10 @@
 	adc	xh, r2, xh, lsr r4
 	orrs	lr, lr, r3, lsl #1
 	biceq	xl, xl, r3, lsr #31
+#ifdef __MAVERICK__
+    cfmvdlr mvd0, xl
+    cfmvdhr mvd0, xh
+#endif
 	RETLDM	"r4, r5, r6"
 
 	@ shift result right of 21 to 31 bits, or left 11 to 1 bits after
@@ -735,6 +760,10 @@
 	adc	xh, xh, #0
 	orrs	lr, lr, r3, lsl #1
 	biceq	xl, xl, r3, lsr #31
+#ifdef __MAVERICK__
+    cfmvdlr mvd0, xl
+    cfmvdhr mvd0, xh
+#endif
 	RETLDM	"r4, r5, r6"
 
 	@ Shift value right of 32 to 64 bits, or 0 to 32 bits after a switch
@@ -749,6 +778,10 @@
 	add	xl, xl, r3, lsr #31
 	orrs	lr, lr, r3, lsl #1
 	biceq	xl, xl, r3, lsr #31
+#ifdef __MAVERICK__
+    cfmvdlr mvd0, xl
+    cfmvdhr mvd0, xh
+#endif
 	RETLDM	"r4, r5, r6"
 
 	@ One or both arguments are denormalized.
@@ -791,6 +824,10 @@
 	eor	xh, xh, yh
 	bic	xh, xh, #0x7fffffff
 	mov	xl, #0
+#ifdef __MAVERICK__
+    cfmvdlr mvd0, xl
+    cfmvdhr mvd0, xh
+#endif
 	RETLDM	"r4, r5, r6"
 
 1:	@ One or both args are INF or NAN.
@@ -820,12 +857,20 @@
 	orr	xh, xh, #0x7f000000
 	orr	xh, xh, #0x00f00000
 	mov	xl, #0
+#ifdef __MAVERICK__
+    cfmvdlr mvd0, xl
+    cfmvdhr mvd0, xh
+#endif
 	RETLDM	"r4, r5, r6"
 
 	@ Return a quiet NAN.
 LSYM(Lml_n):
 	orr	xh, xh, #0x7f000000
 	orr	xh, xh, #0x00f80000
+#ifdef __MAVERICK__
+    cfmvdlr mvd0, xl
+    cfmvdhr mvd0, xh
+#endif
 	RETLDM	"r4, r5, r6"
 
 	FUNC_END aeabi_dmul
diff -ru gcc-4.2.0/gcc/config/arm/ieee754-sf.S gcc-4.2.0-futaris/gcc/config/arm/ieee754-sf.S
--- gcc-4.2.0/gcc/config/arm/ieee754-sf.S	2005-08-06 14:26:35.000000000 +0100
+++ gcc-4.2.0-futaris/gcc/config/arm/ieee754-sf.S	2007-08-27 14:28:07.000000000 +0100
@@ -302,8 +302,13 @@
 
 	orrs	r2, r0, r1
 #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPA_FP__)
 	mvfeqs	f0, #0.0
 #endif
+#if defined (__MAVERICK__)
+    cfmvsr  mvf0, #0.0
+#endif
+#endif
 	RETc(eq)
 
 	mov	r3, #0
@@ -314,8 +319,13 @@
 
 	orrs	r2, r0, r1
 #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPA_FP__)
 	mvfeqs	f0, #0.0
 #endif
+#if defined (__MAVERICK__)
+    cfmvsr  mvf0, #0.0
+#endif
+#endif
 	RETc(eq)
 
 	ands	r3, ah, #0x80000000	@ sign bit in r3
@@ -387,8 +397,13 @@
 #if !defined (__VFP_FP__) && !defined(__SOFTFP__)
 
 LSYM(f0_ret):
+#if defined (__FPA_FP__)
 	str	r0, [sp, #-4]!
 	ldfs	f0, [sp], #4
+#endif
+#if defined (__MAVERICK__)
+    cfmvsr  mvf0, r0
+#endif
 	RETLDM
 
 #endif
@@ -503,6 +518,9 @@
 	@ Check if denormalized result is possible, otherwise return signed 0.
 	cmn	r2, #(24 + 1)
 	bicle	r0, r0, #0x7fffffff
+#ifdef __MAVERICK__
+    cfmvsr  mvf0, r0
+#endif
 	RETc(le)
 
 	@ Shift value right, round, etc.
@@ -515,6 +533,9 @@
 	adc	r0, r0, #0
 	orrs	r3, r3, ip, lsl #1
 	biceq	r0, r0, ip, lsr #31
+#ifdef __MAVERICK__
+    cfmvsr  mvf0, r0
+#endif
 	RET
 
 	@ One or both arguments are denormalized.
@@ -552,6 +573,9 @@
 LSYM(Lml_z):
 	eor	r0, r0, r1
 	bic	r0, r0, #0x7fffffff
+#ifdef __MAVERICK__
+    cfmvsr  mvf0, r0 
+#endif
 	RET
 
 1:	@ One or both args are INF or NAN.
@@ -580,12 +604,18 @@
 	and	r0, r0, #0x80000000
 	orr	r0, r0, #0x7f000000
 	orr	r0, r0, #0x00800000
+#ifdef __MAVERICK__
+    cfmvsr  mvf0, r0
+#endif
 	RET
 
 	@ Return a quiet NAN.
 LSYM(Lml_n):
 	orr	r0, r0, #0x7f000000
 	orr	r0, r0, #0x00c00000
+#ifdef __MAVERICK__
+    cfmvsr  mvf0, r0
+#endif
 	RET
 
 	FUNC_END aeabi_fmul
@@ -662,6 +692,9 @@
 	adds	r2, r2, #127
 	rsbgts	r3, r2, #255
 	orrgt	r0, r0, r2, lsl #23
+#ifdef __MAVERICK__
+    cfmvsr  mvf0, r0
+#endif
 	RETc(gt)
 
 	orr	r0, r0, #0x00800000
diff -ru gcc-4.2.0/gcc/config/arm/lib1funcs.asm gcc-4.2.0-futaris/gcc/config/arm/lib1funcs.asm
--- gcc-4.2.0/gcc/config/arm/lib1funcs.asm	2006-01-18 20:39:17.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/config/arm/lib1funcs.asm	2007-08-27 14:22:51.000000000 +0100
@@ -995,10 +995,24 @@
 	.code	32
 	FUNC_START div0
 
+#if ! defined __thumb__
 	stmfd	sp!, {r1, lr}
 	mov	r0, #SIGFPE
 	bl	SYM(raise) __PLT__
 	RETLDM	r1
+#else
+       push    {r1, lr}
+	mov	r0, #SIGFPE
+	bl	SYM(raise) __PLT__
+#if __ARM_ARCH__ > 4
+       pop     {r1, pc}
+#else
+       @ on 4T that won't work
+       pop     {r1}
+       pop     {r3}
+       bx      r3
+#endif
+#endif
 
 	FUNC_END div0
 	
@@ -1146,11 +1160,12 @@
    code here switches to the correct mode before executing the function.  */
 	
 	.text
-	.align 0
+	.align 1
         .force_thumb
 
 .macro call_via register
 	THUMB_FUNC_START _call_via_\register
+       .hidden SYM (_call_via_\register)
 
 	bx	\register
 	nop
@@ -1247,6 +1262,7 @@
 	.code	16
 
 	THUMB_FUNC_START _interwork_call_via_\register
+       .hidden SYM (_interwork_call_via_\register)
 
 	bx	pc
 	nop
Only in gcc-4.2.0-futaris/gcc/config/arm: lib1funcs.asm.orig
diff -ru gcc-4.2.0/gcc/config/arm/linux-eabi.h gcc-4.2.0-futaris/gcc/config/arm/linux-eabi.h
--- gcc-4.2.0/gcc/config/arm/linux-eabi.h	2006-02-16 23:29:10.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/config/arm/linux-eabi.h	2007-08-27 14:22:51.000000000 +0100
@@ -45,7 +45,7 @@
    The ARM10TDMI core is the default for armv5t, so set
    SUBTARGET_CPU_DEFAULT to achieve this.  */
 #undef SUBTARGET_CPU_DEFAULT
-#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm10tdmi
+#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm9tdmi
 
 #undef SUBTARGET_EXTRA_LINK_SPEC
 #define SUBTARGET_EXTRA_LINK_SPEC " -m armelf_linux_eabi"
diff -ru gcc-4.2.0/gcc/config/arm/linux-elf.h gcc-4.2.0-futaris/gcc/config/arm/linux-elf.h
--- gcc-4.2.0/gcc/config/arm/linux-elf.h	2006-02-16 23:29:10.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/config/arm/linux-elf.h	2007-08-27 14:22:51.000000000 +0100
@@ -28,19 +28,33 @@
 #undef  TARGET_VERSION
 #define TARGET_VERSION  fputs (" (ARM GNU/Linux with ELF)", stderr);
 
+/*
+ * 'config.gcc' defines TARGET_BIG_ENDIAN_DEFAULT as 1 for arm*b-*
+ * (big endian) configurations.
+ */
+#if TARGET_BIG_ENDIAN_DEFAULT
+#define TARGET_ENDIAN_DEFAULT MASK_BIG_END
+#define TARGET_ENDIAN_OPTION "mbig-endian"
+#define TARGET_LINKER_EMULATION "armelfb_linux"
+#else
+#define TARGET_ENDIAN_DEFAULT 0
+#define TARGET_ENDIAN_OPTION "mlittle-endian"
+#define TARGET_LINKER_EMULATION "armelf_linux"
+#endif
+
 #undef  TARGET_DEFAULT_FLOAT_ABI
 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_HARD
 
 #undef  TARGET_DEFAULT
-#define TARGET_DEFAULT (0)
+#define TARGET_DEFAULT (TARGET_ENDIAN_DEFAULT)
 
 #define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm6
 
-#define SUBTARGET_EXTRA_LINK_SPEC " -m armelf_linux -p"
+#define SUBTARGET_EXTRA_LINK_SPEC " -m " TARGET_LINKER_EMULATION " -p"
 
 #undef  MULTILIB_DEFAULTS
 #define MULTILIB_DEFAULTS \
-	{ "marm", "mlittle-endian", "mhard-float", "mno-thumb-interwork" }
+	{ "marm", TARGET_ENDIAN_OPTION, "mhard-float", "mno-thumb-interwork" }
 
 /* Now we define the strings used to build the spec file.  */
 #undef  LIB_SPEC
@@ -49,7 +63,7 @@
    %{shared:-lc} \
    %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
 
-#define LIBGCC_SPEC "%{msoft-float:-lfloat} %{mfloat-abi=soft*:-lfloat} -lgcc"
+#define LIBGCC_SPEC "-lgcc"
 
 #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
 
@@ -61,7 +75,7 @@
    %{rdynamic:-export-dynamic} \
    %{!dynamic-linker:-dynamic-linker " LINUX_DYNAMIC_LINKER "} \
    -X \
-   %{mbig-endian:-EB}" \
+   %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
    SUBTARGET_EXTRA_LINK_SPEC
 
 #undef  LINK_SPEC
Only in gcc-4.2.0-futaris/gcc/config/arm: linux-elf.h.orig
diff -ru gcc-4.2.0/gcc/config/arm/linux-gas.h gcc-4.2.0-futaris/gcc/config/arm/linux-gas.h
--- gcc-4.2.0/gcc/config/arm/linux-gas.h	2007-04-16 21:16:13.000000000 +0100
+++ gcc-4.2.0-futaris/gcc/config/arm/linux-gas.h	2007-08-27 14:22:51.000000000 +0100
@@ -44,6 +44,7 @@
 
 /* Clear the instruction cache from `beg' to `end'.  This makes an
    inline system call to SYS_cacheflush.  */
+#if !defined(__thumb__)
 #define CLEAR_INSN_CACHE(BEG, END)					\
 {									\
   register unsigned long _beg __asm ("a1") = (unsigned long) (BEG);	\
@@ -53,3 +54,18 @@
 		    : "=r" (_beg)					\
 		    : "0" (_beg), "r" (_end), "r" (_flg));		\
 }
+#else
+#define CLEAR_INSN_CACHE(BEG, END)					\
+{									\
+  register unsigned long _beg __asm ("a1") = (unsigned long) (BEG);	\
+  register unsigned long _end __asm ("a2") = (unsigned long) (END);	\
+  register unsigned long _flg __asm ("a3") = 0;				\
+  register unsigned long _swi __asm ("a4") = 0xf0002;			\
+  __asm __volatile ("push      {r7}\n"                                 \
+               "       mov     r7,a4\n"                                \
+               "       swi     0       @ sys_cacheflush\n"             \
+               "       pop     {r7}\n"                                 \
+                   : "=r" (_beg)                                       \
+                   : "0" (_beg), "r" (_end), "r" (_flg), "r" (_swi));  \
+}
+#endif
diff -ru gcc-4.2.0/gcc/config/arm/predicates.md gcc-4.2.0-futaris/gcc/config/arm/predicates.md
--- gcc-4.2.0/gcc/config/arm/predicates.md	2005-12-15 16:42:10.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/config/arm/predicates.md	2007-08-27 14:28:08.000000000 +0100
@@ -182,6 +182,10 @@
 (define_special_predicate "arm_comparison_operator"
   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
 
+;; True for comparisons other than GE, GEU, UNLT, UNORDERED or ORDERED - TODO add LTGT and UNEQ - needs extra support elsewhere 
+(define_special_predicate "maverick_comparison_operator"
+(match_code "eq,ne,le,lt,gt,gtu,leu,ltu,unle,unge,ungt"))
+
 (define_special_predicate "minmax_operator"
   (and (match_code "smin,smax,umin,umax")
        (match_test "mode == GET_MODE (op)")))
Only in gcc-4.2.0-futaris/gcc/config/arm: predicates.md.orig
diff -ru gcc-4.2.0/gcc/config/arm/t-linux gcc-4.2.0-futaris/gcc/config/arm/t-linux
--- gcc-4.2.0/gcc/config/arm/t-linux	2004-05-15 13:41:35.000000000 +0100
+++ gcc-4.2.0-futaris/gcc/config/arm/t-linux	2007-08-27 14:22:51.000000000 +0100
@@ -4,7 +4,11 @@
 LIBGCC2_DEBUG_CFLAGS = -g0
 
 LIB1ASMSRC = arm/lib1funcs.asm
-LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx
+LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx \
+    _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \
+    _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \
+    _call_via_rX \
+    _fixsfsi _fixunssfsi _floatdidf _floatdisf
 
 # MULTILIB_OPTIONS = mhard-float/msoft-float
 # MULTILIB_DIRNAMES = hard-float soft-float
diff -ru gcc-4.2.0/gcc/config/cris/linux.h gcc-4.2.0-futaris/gcc/config/cris/linux.h
--- gcc-4.2.0/gcc/config/cris/linux.h	2006-02-18 11:12:51.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/config/cris/linux.h	2007-08-27 14:22:50.000000000 +0100
@@ -74,7 +74,11 @@
 #define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
 
 #undef CRIS_SUBTARGET_VERSION
-#define CRIS_SUBTARGET_VERSION " - cris-axis-linux-gnu"
+#if UCLIBC_DEFAULT
+# define CRIS_SUBTARGET_VERSION " - cris-axis-linux-uclibc"
+#else
+# define CRIS_SUBTARGET_VERSION " - cris-axis-linux-gnu"
+#endif
 
 #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
 
diff -ru gcc-4.2.0/gcc/config.gcc gcc-4.2.0-futaris/gcc/config.gcc
--- gcc-4.2.0/gcc/config.gcc	2007-02-03 05:25:20.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/config.gcc	2007-08-27 14:22:51.000000000 +0100
@@ -705,6 +705,11 @@
 	tm_file="dbxelf.h elfos.h linux.h arm/elf.h arm/linux-gas.h arm/linux-elf.h"
 	tmake_file="${tmake_file} t-linux arm/t-arm"
 	case ${target} in
+	arm*b-*)
+		tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+		;;
+	esac
+	case ${target} in
 	arm*-*-linux-*eabi)
 	    tm_file="$tm_file arm/bpabi.h arm/linux-eabi.h"
 	    tmake_file="$tmake_file arm/t-arm-elf arm/t-bpabi arm/t-linux-eabi"
Only in gcc-4.2.0-futaris/gcc: config.gcc.orig
diff -ru gcc-4.2.0/gcc/configure gcc-4.2.0-futaris/gcc/configure
--- gcc-4.2.0/gcc/configure	2007-01-02 03:44:31.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/configure	2007-08-27 14:28:07.000000000 +0100
@@ -12716,7 +12716,7 @@
 	esac
 	saved_CFLAGS="${CFLAGS}"
 	CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
-	${realsrcdir}/configure \
+	CONFIG_SITE= ${realsrcdir}/configure --cache-file=./other.cache \
 		--enable-languages=${enable_languages-all} \
 		--target=$target_alias --host=$build_alias --build=$build_alias
 	CFLAGS="${saved_CFLAGS}"
@@ -14564,7 +14564,7 @@
 	tls_first_minor=14
 	tls_as_opt="-m64 -Aesame --fatal-warnings"
 	;;
-  sh-*-* | sh[34]-*-*)
+  sh-*-* | sh[34]*-*-*)
     conftest_s='
 	.section ".tdata","awT",@progbits
 foo:	.long	25
diff -ru gcc-4.2.0/gcc/configure.ac gcc-4.2.0-futaris/gcc/configure.ac
--- gcc-4.2.0/gcc/configure.ac	2007-01-02 03:44:31.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/configure.ac	2007-08-27 14:22:51.000000000 +0100
@@ -2538,7 +2538,7 @@
 	tls_first_minor=14
 	tls_as_opt="-m64 -Aesame --fatal-warnings"
 	;;
-  sh-*-* | sh[34]-*-*)
+  sh-*-* | sh[34]*-*-*)
     conftest_s='
 	.section ".tdata","awT",@progbits
 foo:	.long	25
Only in gcc-4.2.0-futaris/gcc: configure.ac.orig
Only in gcc-4.2.0-futaris/gcc: configure.orig
diff -ru gcc-4.2.0/gcc/doc/invoke.texi gcc-4.2.0-futaris/gcc/doc/invoke.texi
--- gcc-4.2.0/gcc/doc/invoke.texi	2007-04-24 22:54:22.000000000 +0100
+++ gcc-4.2.0-futaris/gcc/doc/invoke.texi	2007-08-27 14:28:08.000000000 +0100
@@ -416,7 +416,7 @@
 -msingle-pic-base  -mno-single-pic-base @gol
 -mpic-register=@var{reg} @gol
 -mnop-fun-dllimport @gol
--mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol
+-mfix-crunch-d0 -mfix-crunch-d1 @gol
 -mpoke-function-name @gol
 -mthumb  -marm @gol
 -mtpcs-frame  -mtpcs-leaf-frame @gol
@@ -7724,17 +7724,12 @@
 Specify the register to be used for PIC addressing.  The default is R10
 unless stack-checking is enabled, when R9 is used.
 
-@item -mcirrus-fix-invalid-insns
-@opindex mcirrus-fix-invalid-insns
-@opindex mno-cirrus-fix-invalid-insns
-Insert NOPs into the instruction stream to in order to work around
-problems with invalid Maverick instruction combinations.  This option
-is only valid if the @option{-mcpu=ep9312} option has been used to
-enable generation of instructions for the Cirrus Maverick floating
-point co-processor.  This option is not enabled by default, since the
-problem is only present in older Maverick implementations.  The default
-can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
-switch.
+@item -mfix-crunch-d0
+@itemx -mfix-crunch-d1
+@opindex mfix-crunch-d0
+@opindex mfix-crunch-d1
+Enable workarounds for the Cirrus MaverickCrunch coprocessor revisions
+D0 and D1 respectively.
 
 @item -mpoke-function-name
 @opindex mpoke-function-name
Only in gcc-4.2.0-futaris/gcc/doc: invoke.texi.orig
diff -ru gcc-4.2.0/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c gcc-4.2.0-futaris/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c
--- gcc-4.2.0/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c	2003-02-03 10:15:15.000000000 +0000
+++ gcc-4.2.0-futaris/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c	2007-08-27 14:28:07.000000000 +0100
@@ -49,7 +49,7 @@
     exit (0);
   
   c(0x3690000000000000ULL, 0x00000000U);
-#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__)
+#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__) && ! (defined __MAVERICK__)
   /* The ARM always stores FP numbers in big-wordian format,
      even when running in little-byteian mode.  */
   c(0x0000000136900000ULL, 0x00000001U);
diff -ru gcc-4.2.0/libffi/configure gcc-4.2.0-futaris/libffi/configure
--- gcc-4.2.0/libffi/configure	2007-05-14 04:19:11.000000000 +0100
+++ gcc-4.2.0-futaris/libffi/configure	2007-08-27 14:22:50.000000000 +0100
@@ -3460,7 +3460,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
Only in gcc-4.2.0-futaris/libffi: configure.orig
diff -ru gcc-4.2.0/libgfortran/configure gcc-4.2.0-futaris/libgfortran/configure
--- gcc-4.2.0/libgfortran/configure	2007-05-14 04:19:11.000000000 +0100
+++ gcc-4.2.0-futaris/libgfortran/configure	2007-08-27 14:22:50.000000000 +0100
@@ -3721,7 +3721,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
Only in gcc-4.2.0-futaris/libgfortran: configure.orig
diff -ru gcc-4.2.0/libgomp/configure gcc-4.2.0-futaris/libgomp/configure
--- gcc-4.2.0/libgomp/configure	2007-05-14 04:19:11.000000000 +0100
+++ gcc-4.2.0-futaris/libgomp/configure	2007-08-27 14:22:50.000000000 +0100
@@ -3893,7 +3893,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
Only in gcc-4.2.0-futaris/libgomp: configure.orig
diff -ru gcc-4.2.0/libjava/classpath/configure gcc-4.2.0-futaris/libjava/classpath/configure
--- gcc-4.2.0/libjava/classpath/configure	2007-01-17 18:10:26.000000000 +0000
+++ gcc-4.2.0-futaris/libjava/classpath/configure	2007-08-27 14:22:50.000000000 +0100
@@ -5307,7 +5307,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
Only in gcc-4.2.0-futaris/libjava/classpath: configure.orig
diff -ru gcc-4.2.0/libjava/classpath/ltconfig gcc-4.2.0-futaris/libjava/classpath/ltconfig
--- gcc-4.2.0/libjava/classpath/ltconfig	2006-08-07 21:37:50.000000000 +0100
+++ gcc-4.2.0-futaris/libjava/classpath/ltconfig	2007-08-27 14:22:50.000000000 +0100
@@ -603,7 +603,7 @@
 
 # Transform linux* to *-*-linux-gnu*, to support old configure scripts.
 case $host_os in
-linux-gnu*) ;;
+linux-gnu*|linux-uclibc*) ;;
 linux*) host=`echo $host | sed 's/^\(.*-.*-linux\)\(.*\)$/\1-gnu\2/'`
 esac
 
@@ -1251,7 +1251,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   version_type=linux
   need_lib_prefix=no
   need_version=no
diff -ru gcc-4.2.0/libjava/configure gcc-4.2.0-futaris/libjava/configure
--- gcc-4.2.0/libjava/configure	2007-05-14 04:19:11.000000000 +0100
+++ gcc-4.2.0-futaris/libjava/configure	2007-08-27 14:22:50.000000000 +0100
@@ -5424,7 +5424,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
Only in gcc-4.2.0-futaris/libjava: configure.orig
diff -ru gcc-4.2.0/libmudflap/configure gcc-4.2.0-futaris/libmudflap/configure
--- gcc-4.2.0/libmudflap/configure	2006-12-04 11:13:07.000000000 +0000
+++ gcc-4.2.0-futaris/libmudflap/configure	2007-08-27 14:22:50.000000000 +0100
@@ -5394,7 +5394,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
Only in gcc-4.2.0-futaris/libmudflap: configure.orig
diff -ru gcc-4.2.0/libobjc/configure gcc-4.2.0-futaris/libobjc/configure
--- gcc-4.2.0/libobjc/configure	2006-10-15 08:42:57.000000000 +0100
+++ gcc-4.2.0-futaris/libobjc/configure	2007-08-27 14:22:50.000000000 +0100
@@ -3314,7 +3314,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
Only in gcc-4.2.0-futaris/libobjc: configure.orig
diff -ru gcc-4.2.0/libssp/configure gcc-4.2.0-futaris/libssp/configure
--- gcc-4.2.0/libssp/configure	2006-10-15 08:42:57.000000000 +0100
+++ gcc-4.2.0-futaris/libssp/configure	2007-08-27 14:22:50.000000000 +0100
@@ -4480,7 +4480,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
Only in gcc-4.2.0-futaris/libssp: configure.orig
diff -ru gcc-4.2.0/libstdc++-v3/acinclude.m4 gcc-4.2.0-futaris/libstdc++-v3/acinclude.m4
--- gcc-4.2.0/libstdc++-v3/acinclude.m4	2007-03-05 16:44:44.000000000 +0000
+++ gcc-4.2.0-futaris/libstdc++-v3/acinclude.m4	2007-08-27 14:22:50.000000000 +0100
@@ -1337,7 +1337,7 @@
   AC_MSG_CHECKING([for C locale to use])
   GLIBCXX_ENABLE(clocale,auto,[@<:@=MODEL@:>@],
     [use MODEL for target locale package],
-    [permit generic|gnu|ieee_1003.1-2001|yes|no|auto])
+    [permit generic|gnu|ieee_1003.1-2001|uclibc|yes|no|auto])
   
   # If they didn't use this option switch, or if they specified --enable
   # with no specific model, we'll have to look for one.  If they
@@ -1353,6 +1353,9 @@
   # Default to "generic".
   if test $enable_clocale_flag = auto; then
     case ${target_os} in
+      *-uclibc*)
+        enable_clocale_flag=uclibc
+        ;;
       linux* | gnu* | kfreebsd*-gnu | knetbsd*-gnu)
         AC_EGREP_CPP([_GLIBCXX_ok], [
         #include <features.h>
@@ -1496,6 +1499,40 @@
       CTIME_CC=config/locale/generic/time_members.cc
       CLOCALE_INTERNAL_H=config/locale/generic/c++locale_internal.h
       ;;
+    uclibc)
+      AC_MSG_RESULT(uclibc)
+
+      # Declare intention to use gettext, and add support for specific
+      # languages.
+      # For some reason, ALL_LINGUAS has to be before AM-GNU-GETTEXT
+      ALL_LINGUAS="de fr"
+
+      # Don't call AM-GNU-GETTEXT here. Instead, assume glibc.
+      AC_CHECK_PROG(check_msgfmt, msgfmt, yes, no)
+      if test x"$check_msgfmt" = x"yes" && test x"$enable_nls" = x"yes"; then
+        USE_NLS=yes
+      fi
+      # Export the build objects.
+      for ling in $ALL_LINGUAS; do \
+        glibcxx_MOFILES="$glibcxx_MOFILES $ling.mo"; \
+        glibcxx_POFILES="$glibcxx_POFILES $ling.po"; \
+      done
+      AC_SUBST(glibcxx_MOFILES)
+      AC_SUBST(glibcxx_POFILES)
+
+      CLOCALE_H=config/locale/uclibc/c_locale.h
+      CLOCALE_CC=config/locale/uclibc/c_locale.cc
+      CCODECVT_CC=config/locale/uclibc/codecvt_members.cc
+      CCOLLATE_CC=config/locale/uclibc/collate_members.cc
+      CCTYPE_CC=config/locale/uclibc/ctype_members.cc
+      CMESSAGES_H=config/locale/uclibc/messages_members.h
+      CMESSAGES_CC=config/locale/uclibc/messages_members.cc
+      CMONEY_CC=config/locale/uclibc/monetary_members.cc
+      CNUMERIC_CC=config/locale/uclibc/numeric_members.cc
+      CTIME_H=config/locale/uclibc/time_members.h
+      CTIME_CC=config/locale/uclibc/time_members.cc
+      CLOCALE_INTERNAL_H=config/locale/uclibc/c++locale_internal.h
+      ;;
   esac
 
   # This is where the testsuite looks for locale catalogs, using the
Only in gcc-4.2.0-futaris/libstdc++-v3: acinclude.m4.orig
Only in gcc-4.2.0-futaris/libstdc++-v3/config/locale: uclibc
diff -ru gcc-4.2.0/libstdc++-v3/configure gcc-4.2.0-futaris/libstdc++-v3/configure
--- gcc-4.2.0/libstdc++-v3/configure	2007-03-05 16:44:44.000000000 +0000
+++ gcc-4.2.0-futaris/libstdc++-v3/configure	2007-08-27 14:22:51.000000000 +0100
@@ -4283,7 +4283,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
@@ -5771,7 +5771,7 @@
   enableval="$enable_clocale"
 
       case "$enableval" in
-       generic|gnu|ieee_1003.1-2001|yes|no|auto) ;;
+       generic|gnu|ieee_1003.1-2001|uclibc|yes|no|auto) ;;
        *) { { echo "$as_me:$LINENO: error: Unknown argument to enable/disable clocale" >&5
 echo "$as_me: error: Unknown argument to enable/disable clocale" >&2;}
    { (exit 1); exit 1; }; } ;;
@@ -5796,6 +5796,9 @@
   # Default to "generic".
   if test $enable_clocale_flag = auto; then
     case ${target_os} in
+      linux-uclibc*)
+        enable_clocale_flag=uclibc
+	;;
       linux* | gnu* | kfreebsd*-gnu | knetbsd*-gnu)
         cat >conftest.$ac_ext <<_ACEOF
 /* confdefs.h.  */
@@ -6026,6 +6029,76 @@
       CTIME_CC=config/locale/generic/time_members.cc
       CLOCALE_INTERNAL_H=config/locale/generic/c++locale_internal.h
       ;;
+    uclibc)
+      echo "$as_me:$LINENO: result: uclibc" >&5
+echo "${ECHO_T}uclibc" >&6
+
+      # Declare intention to use gettext, and add support for specific
+      # languages.
+      # For some reason, ALL_LINGUAS has to be before AM-GNU-GETTEXT
+      ALL_LINGUAS="de fr"
+
+      # Don't call AM-GNU-GETTEXT here. Instead, assume glibc.
+      # Extract the first word of "msgfmt", so it can be a program name with args.
+set dummy msgfmt; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_check_msgfmt+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if test -n "$check_msgfmt"; then
+  ac_cv_prog_check_msgfmt="$check_msgfmt" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_check_msgfmt="yes"
+    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+
+  test -z "$ac_cv_prog_check_msgfmt" && ac_cv_prog_check_msgfmt="no"
+fi
+fi
+check_msgfmt=$ac_cv_prog_check_msgfmt
+if test -n "$check_msgfmt"; then
+  echo "$as_me:$LINENO: result: $check_msgfmt" >&5
+echo "${ECHO_T}$check_msgfmt" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+      if test x"$check_msgfmt" = x"yes" && test x"$enable_nls" = x"yes"; then
+        USE_NLS=yes
+      fi
+      # Export the build objects.
+      for ling in $ALL_LINGUAS; do \
+        glibcxx_MOFILES="$glibcxx_MOFILES $ling.mo"; \
+        glibcxx_POFILES="$glibcxx_POFILES $ling.po"; \
+      done
+
+
+
+      CLOCALE_H=config/locale/uclibc/c_locale.h
+      CLOCALE_CC=config/locale/uclibc/c_locale.cc
+      CCODECVT_CC=config/locale/uclibc/codecvt_members.cc
+      CCOLLATE_CC=config/locale/uclibc/collate_members.cc
+      CCTYPE_CC=config/locale/uclibc/ctype_members.cc
+      CMESSAGES_H=config/locale/uclibc/messages_members.h
+      CMESSAGES_CC=config/locale/uclibc/messages_members.cc
+      CMONEY_CC=config/locale/uclibc/monetary_members.cc
+      CNUMERIC_CC=config/locale/uclibc/numeric_members.cc
+      CTIME_H=config/locale/uclibc/time_members.h
+      CTIME_CC=config/locale/uclibc/time_members.cc
+      CLOCALE_INTERNAL_H=config/locale/uclibc/c++locale_internal.h
+      ;;
   esac
 
   # This is where the testsuite looks for locale catalogs, using the
@@ -7277,6 +7350,9 @@
 cat >>conftest.$ac_ext <<_ACEOF
 /* end confdefs.h.  */
 #include <complex.h>
+#ifdef __UCLIBC__
+#error ugly hack to make sure configure test fails here for cross until uClibc supports the complex funcs
+#endif
 int
 main ()
 {
Only in gcc-4.2.0-futaris/libstdc++-v3: configure.orig
diff -ru gcc-4.2.0/libstdc++-v3/fragment.am gcc-4.2.0-futaris/libstdc++-v3/fragment.am
--- gcc-4.2.0/libstdc++-v3/fragment.am	2005-03-21 17:40:24.000000000 +0000
+++ gcc-4.2.0-futaris/libstdc++-v3/fragment.am	2007-08-27 14:22:51.000000000 +0100
@@ -21,5 +21,5 @@
 	$(WARN_FLAGS) $(WERROR) -fdiagnostics-show-location=once
 
 # -I/-D flags to pass when compiling.
-AM_CPPFLAGS = $(GLIBCXX_INCLUDES)
+AM_CPPFLAGS = $(GLIBCXX_INCLUDES) -I$(toplevel_srcdir)/include
 
diff -ru gcc-4.2.0/libstdc++-v3/include/c_compatibility/wchar.h gcc-4.2.0-futaris/libstdc++-v3/include/c_compatibility/wchar.h
--- gcc-4.2.0/libstdc++-v3/include/c_compatibility/wchar.h	2005-08-17 03:28:44.000000000 +0100
+++ gcc-4.2.0-futaris/libstdc++-v3/include/c_compatibility/wchar.h	2007-08-27 14:22:50.000000000 +0100
@@ -101,7 +101,9 @@
 using std::wmemcpy;
 using std::wmemmove;
 using std::wmemset;
+#if _GLIBCXX_HAVE_WCSFTIME
 using std::wcsftime;
+#endif
 
 #if _GLIBCXX_USE_C99
 using std::wcstold;
diff -ru gcc-4.2.0/libstdc++-v3/include/c_std/std_cstdio.h gcc-4.2.0-futaris/libstdc++-v3/include/c_std/std_cstdio.h
--- gcc-4.2.0/libstdc++-v3/include/c_std/std_cstdio.h	2006-12-07 09:33:51.000000000 +0000
+++ gcc-4.2.0-futaris/libstdc++-v3/include/c_std/std_cstdio.h	2007-08-27 14:22:51.000000000 +0100
@@ -144,7 +144,7 @@
 
 _GLIBCXX_END_NAMESPACE
 
-#if _GLIBCXX_USE_C99
+#if _GLIBCXX_USE_C99 || defined(__UCLIBC__)
 
 #undef snprintf
 #undef vfscanf
Only in gcc-4.2.0-futaris/libstdc++-v3/include/c_std: std_cstdio.h.orig
diff -ru gcc-4.2.0/libstdc++-v3/include/c_std/std_cwchar.h gcc-4.2.0-futaris/libstdc++-v3/include/c_std/std_cwchar.h
--- gcc-4.2.0/libstdc++-v3/include/c_std/std_cwchar.h	2006-12-07 09:33:51.000000000 +0000
+++ gcc-4.2.0-futaris/libstdc++-v3/include/c_std/std_cwchar.h	2007-08-27 14:22:50.000000000 +0100
@@ -182,7 +182,9 @@
   using ::wcscoll;
   using ::wcscpy;
   using ::wcscspn;
+#if _GLIBCXX_HAVE_WCSFTIME
   using ::wcsftime;
+#endif
   using ::wcslen;
   using ::wcsncat;
   using ::wcsncmp;
diff -ru gcc-4.2.0/libstdc++-v3/include/ext/rope gcc-4.2.0-futaris/libstdc++-v3/include/ext/rope
--- gcc-4.2.0/libstdc++-v3/include/ext/rope	2006-10-17 12:56:21.000000000 +0100
+++ gcc-4.2.0-futaris/libstdc++-v3/include/ext/rope	2007-08-27 14:22:51.000000000 +0100
@@ -58,6 +58,9 @@
 #include <bits/allocator.h>
 #include <ext/hash_fun.h>
 
+/* cope w/ index defined as macro, SuSv3 proposal */
+#undef index
+
 # ifdef __GC
 #   define __GC_CONST const
 # else
diff -ru gcc-4.2.0/libstdc++-v3/include/ext/ropeimpl.h gcc-4.2.0-futaris/libstdc++-v3/include/ext/ropeimpl.h
--- gcc-4.2.0/libstdc++-v3/include/ext/ropeimpl.h	2006-10-17 12:56:21.000000000 +0100
+++ gcc-4.2.0-futaris/libstdc++-v3/include/ext/ropeimpl.h	2007-08-27 14:22:51.000000000 +0100
@@ -54,6 +54,9 @@
 #include <ext/memory> // For uninitialized_copy_n
 #include <ext/numeric> // For power
 
+/* cope w/ index defined as macro, SuSv3 proposal */
+#undef index
+
 _GLIBCXX_BEGIN_NAMESPACE(__gnu_cxx)
 
   using std::size_t;
Only in gcc-4.2.0-futaris/libstdc++-v3/include/ext: ropeimpl.h.orig
Only in gcc-4.2.0-futaris/libstdc++-v3/include/ext: rope.orig
diff -ru gcc-4.2.0/libstdc++-v3/libmath/Makefile.am gcc-4.2.0-futaris/libstdc++-v3/libmath/Makefile.am
--- gcc-4.2.0/libstdc++-v3/libmath/Makefile.am	2005-08-17 03:28:44.000000000 +0100
+++ gcc-4.2.0-futaris/libstdc++-v3/libmath/Makefile.am	2007-08-27 14:22:51.000000000 +0100
@@ -35,7 +35,7 @@
 
 libmath_la_SOURCES = stubs.c
 
-AM_CPPFLAGS = $(CANADIAN_INCLUDES)
+AM_CPPFLAGS = $(CANADIAN_INCLUDES) -I$(toplevel_srcdir)/include
 
 # Only compiling "C" sources in this directory.
 LIBTOOL = @LIBTOOL@ --tag CC
diff -ru gcc-4.2.0/libstdc++-v3/src/Makefile.am gcc-4.2.0-futaris/libstdc++-v3/src/Makefile.am
--- gcc-4.2.0/libstdc++-v3/src/Makefile.am	2006-07-28 05:57:34.000000000 +0100
+++ gcc-4.2.0-futaris/libstdc++-v3/src/Makefile.am	2007-08-27 14:22:50.000000000 +0100
@@ -257,6 +257,10 @@
 	  $(OPT_LDFLAGS) $(SECTION_LDFLAGS) $(AM_CXXFLAGS) $(LTLDFLAGS) -o $@
 
 
+install-exec-local:
+	$(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o
+	$(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir)
+
 # Added bits to build debug library.
 if GLIBCXX_BUILD_DEBUG
 all-local: build_debug
Only in gcc-4.2.0-futaris/libstdc++-v3/src: Makefile.am.orig
diff -ru gcc-4.2.0/libstdc++-v3/src/Makefile.in gcc-4.2.0-futaris/libstdc++-v3/src/Makefile.in
--- gcc-4.2.0/libstdc++-v3/src/Makefile.in	2006-10-16 20:08:22.000000000 +0100
+++ gcc-4.2.0-futaris/libstdc++-v3/src/Makefile.in	2007-08-27 14:22:50.000000000 +0100
@@ -657,7 +657,7 @@
 
 install-data-am: install-data-local
 
-install-exec-am: install-toolexeclibLTLIBRARIES
+install-exec-am: install-toolexeclibLTLIBRARIES install-exec-local
 
 install-info: install-info-am
 
@@ -690,6 +690,7 @@
 	distclean-libtool distclean-tags distdir dvi dvi-am html \
 	html-am info info-am install install-am install-data \
 	install-data-am install-data-local install-exec \
+	install-exec-local \
 	install-exec-am install-info install-info-am install-man \
 	install-strip install-toolexeclibLTLIBRARIES installcheck \
 	installcheck-am installdirs maintainer-clean \
@@ -799,6 +800,11 @@
 install_debug:
 	(cd ${debugdir} && $(MAKE) \
 	toolexeclibdir=$(glibcxx_toolexeclibdir)/debug install)
+
+install-exec-local:
+	$(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o
+	$(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir)
+
 # Tell versions [3.59,3.63) of GNU make to not export all variables.
 # Otherwise a system limit (for SysV at least) may be exceeded.
 .NOEXPORT:
Only in gcc-4.2.0-futaris/libstdc++-v3/src: Makefile.in.orig
diff -ru gcc-4.2.0/libtool.m4 gcc-4.2.0-futaris/libtool.m4
--- gcc-4.2.0/libtool.m4	2005-07-16 03:30:53.000000000 +0100
+++ gcc-4.2.0-futaris/libtool.m4	2007-08-27 14:22:50.000000000 +0100
@@ -739,7 +739,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
diff -ru gcc-4.2.0/ltconfig gcc-4.2.0-futaris/ltconfig
--- gcc-4.2.0/ltconfig	2007-02-14 17:08:35.000000000 +0000
+++ gcc-4.2.0-futaris/ltconfig	2007-08-27 14:22:50.000000000 +0100
@@ -603,7 +603,7 @@
 
 # Transform linux* to *-*-linux-gnu*, to support old configure scripts.
 case $host_os in
-linux-gnu*) ;;
+linux-gnu*|linux-uclibc*) ;;
 linux*) host=`echo $host | sed 's/^\(.*-.*-linux\)\(.*\)$/\1-gnu\2/'`
 esac
 
@@ -1251,7 +1251,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   version_type=linux
   need_lib_prefix=no
   need_version=no
diff -ru gcc-4.2.0/Makefile.in gcc-4.2.0-futaris/Makefile.in
--- gcc-4.2.0/Makefile.in	2006-12-29 17:47:06.000000000 +0000
+++ gcc-4.2.0-futaris/Makefile.in	2007-08-27 14:22:51.000000000 +0100
@@ -194,6 +194,7 @@
 	AS="$(COMPILER_AS_FOR_TARGET)"; export AS; \
 	CC="$(CC_FOR_TARGET)"; export CC; \
 	CFLAGS="$(CFLAGS_FOR_TARGET)"; export CFLAGS; \
+	CPP="$(CC_FOR_TARGET) -E"; export CCP; \
 	CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \
 	CPPFLAGS="$(CPPFLAGS_FOR_TARGET)"; export CPPFLAGS; \
 	CXXFLAGS="$(CXXFLAGS_FOR_TARGET)"; export CXXFLAGS; \
@@ -346,7 +347,7 @@
 CXXFLAGS_FOR_TARGET = $(CXXFLAGS) $(SYSROOT_CFLAGS_FOR_TARGET)
 LIBCFLAGS_FOR_TARGET = $(CFLAGS_FOR_TARGET)
 LIBCXXFLAGS_FOR_TARGET = $(CXXFLAGS_FOR_TARGET) -fno-implicit-templates
-LDFLAGS_FOR_TARGET = 
+LDFLAGS_FOR_TARGET = @LDFLAGS@ 
 PICFLAG_FOR_TARGET = 
 
 # ------------------------------------
Only in gcc-4.2.0-futaris: Makefile.in.orig
diff -ru gcc-4.2.0/Makefile.tpl gcc-4.2.0-futaris/Makefile.tpl
--- gcc-4.2.0/Makefile.tpl	2006-12-29 17:47:06.000000000 +0000
+++ gcc-4.2.0-futaris/Makefile.tpl	2007-08-27 14:22:51.000000000 +0100
@@ -349,7 +349,7 @@
 CXXFLAGS_FOR_TARGET = $(CXXFLAGS) $(SYSROOT_CFLAGS_FOR_TARGET)
 LIBCFLAGS_FOR_TARGET = $(CFLAGS_FOR_TARGET)
 LIBCXXFLAGS_FOR_TARGET = $(CXXFLAGS_FOR_TARGET) -fno-implicit-templates
-LDFLAGS_FOR_TARGET = 
+LDFLAGS_FOR_TARGET = @LDFLAGS@ 
 PICFLAG_FOR_TARGET = 
 
 # ------------------------------------
Only in gcc-4.2.0-futaris: Makefile.tpl.orig
diff -ru gcc-4.2.0/zlib/configure gcc-4.2.0-futaris/zlib/configure
--- gcc-4.2.0/zlib/configure	2007-01-17 18:10:26.000000000 +0000
+++ gcc-4.2.0-futaris/zlib/configure	2007-08-27 14:22:50.000000000 +0100
@@ -3429,7 +3429,7 @@
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
Only in gcc-4.2.0-futaris/zlib: configure.orig